PA72 Series – PXI/PXIe Generator & Digitizer platform
PA72 Base board
The PA72 base board contains a clock generator, trigger
circuitry, a digital voltmeter and the PXI bus interface. In the
block diagram below, the base board functions are yellow and
the daughter board functions are green.
The clock generator is a low jitter PLL clock that has less than
0.5ps jitter for low loop filter bandwidths. With higher loop
filter bandwidths, frequency settling time can be less than
250ms.The main clock frequency ranges from 2kHz up to
945MHz with a resolution of less than 1 kHz. Each daughter
board slot has its own clock divider.
Therefore the clock for each daughter board can be different
while maintaining proper synchronization. The PLL clock
generator features a high stability, low noise and low jitter
10MHz on-board reference clock with 1ppm frequency stability.
In addition the PLL can be locked to the PXI backplane clock or
to an external reference clock. The on-board clock source can
also be bypassed by an external direct clock.
The trigger input supports edge and level triggering and positive
and negative going trigger signals. The trigger source can be
software, PXI Star trigger, PXI Trigger 0-6, or external (front).
Additionally, digitizer boards can be set to edge-trigger on the
analog input signal.
|Frequency range||2kHz to 945MHz|
|Sync possibilities||10MHz backplane or 10MHz external clock|
|PLL lock time||250ms – 1s (depending on loop filter BW)|
External clock input
|Clock rate||DC to 500MHz|
|Treshold level||0V or 1V (programmable)|
|Input impedance||50 Ohm|
Front trigger input
|Threshold level||1 V|
|Input impedance||1k Ohm|
|Max input level||-0.5 V to +5.5 V|
Digitizer’s analog level trigger, Front trigger input, PXI Star, PXI Trig 0..6, Software trigger
|PA72 bus||32-bit PXI, burst mode support|
|PA72e bus||x1 PXI Express, burst mode support|
|Max. burst data rate||132 MByte/s|